The invention relates to a reference voltage generator circuit for a nonvolatile memory, and more particularly to a reference voltage generator circuit for a nonvolatile memory, which, in generating each voltage for write, erase, and verification, can provide temperature characteristics depending upon each operation mode (write/erase, verification/read) by a single band gap circuit.
In nonvolatile semiconductor memories, after erasure or writing, write verification or erase verification is carried out to examine whether or not information has been correctly erased or written, followed by reading operation. To this end, erase verify voltage (or write verify voltage) and read voltage used as gate voltage of the memory cell at the time of erase verification (or write verification) and reading are generated by a reference voltage generator circuit within the nonvolatile semiconductor memory. Voltage is selectively sent to each word line by performing switching among the erase verify voltage, the write verify voltage, and the read voltage.
FIG. 1 shows a specific example of a conventional reference voltage generator circuit for a nonvolatile memory.
A reference voltage generator circuit 500 comprises a band gap (BGR) circuit 510 for generating an output voltage REF and a write regulator circuit 520 connected to the band gap circuit 510. A voltage REF output from the band gap circuit 510 is input into the write regulator circuit 520, and the write regulator circuit 520 generates an output voltage OUT based on this REF. The band gap circuit 510 comprises P-type transistors 1, 4, 6, N-type transistors 2, 5, resistors 3, 7, and a diode 8.
Each source of the P-type transistors 1, 4, 6 is connected to a power line. The gate and the drain of the P-type transistor 1 are commonly bonded, and this portion is connected to the drain of the N-type transistor 2. The gate of the P-type transistor 4 is connected to the drain of the P-type transistor 1, and the drain of the P-type transistor 4 is connected to the drain of the N-type transistor 5. The P-type transistor 6 in its gate is connected to the drain of the P-type transistor 1. A constant current inversely proportional to the resistance value of the resistor 3 is output from the drain of the P-type transistor 6. The P-type transistors 1, 4, 6 are connected to the drain of the N-type transistor 2 in such a state that the gates of these transistors are connected parallel to one another. The source of the N-type transistor 2 is grounded through the resistor 3, and the gate of the N-type transistor 2 is connected to the gate of the N-type transistor 5. The source of the N-type transistor 5 is grounded, and the drain and the gate of the N-type transistor 5 each are connected to the source of the P-type transistor 6. A circuit composed of the resistor 7 and the diode 8, which are connected in series, is inserted between the drain of the P-type transistor 6 and the ground. An output voltage REF is output as an output of the band gap circuit 510 form the high potential side of the resistor 7.
In the band gap circuit 510, a constant current supplied to the series circuit composed of the resistor 7 and the diode 8 is inversely proportional to the resistance value of the resistor 3. For this reason, a voltage drop corresponding to the resistance value of the resistor 3, that is, a voltage drop VR set by the ratio of the resistance value R7 of the resistor 7 to the resistance value R3 of the resistor 3 (=reference value R7/resistance value R3), occurs in the resistor 7. The sum of the voltage drop VR and the forward voltage VF of the diode 8 (=VR+VF) is output as an output voltage REF.
The temperature dependency xcex4(REF)/xcex4T of the output voltage REF is expressed by equation (1):
xcex4(REF3)/xcex4T=(k/q)xc3x97ln[{(W4/L4)xc3x97(W2/L2)}/{(W1/L1)xc3x97(W5/L5)}]xc3x97{(W6/L6)/(W1/L1)}xc3x97(R7/R3)+(xcex4(VF)/xcex4T) xe2x80x83xe2x80x83(1) 
wherein
k represents Boltzmann constant and is 1.38xc3x97exe2x88x9223 [J/K];
q represents the quantity of electric charges of electron in a simple form (elementary electric charge) and is 1.6xc3x97exe2x88x9219 [C];
T represents absolute temperature;
W1, W2, W4, W5, and W6 respectively represent the channel widths of the transistors 1, 2, 4, 5, and 6;
L1, L2, L4, L5, and L6 respectively represent the channel lengths of the transistors 1, 2, 4, 5, and 6; and
k/q is a constant;
R3 represents the resistance value of the resistor 3;
R7 represents the resistance value of the resistor 7; and
VF represents the forward voltage of the diode 8.
This equation (1) shows that the temperature dependency xcex4(VF)/xcex4T of the forward voltage VF of the diode 8 usually has a negative value, and the temperature dependency xcex4(REF)/xcex4T of the output voltage REF can be set by the ratio of the resistance value R7 of the resistor 7 to the resistance value R3 of the resistor 3, i.e., R7/R3. That is, what is required for imparting temperature dependency to the REF level is only to set the resistance value ratio R7/R3.
The write regulator circuit 520 comprises a differential amplifier 9, a P-type transistor 10, and a resistor 11. The output voltage REF of the band gap circuit 510 is input into a (xe2x88x92) input terminal of the differential amplifier 9, and a voltage Sref of a split terminal (split by a resistor R10 and a resistor R11) of the resistor 11 is input into a (+) input terminal. The gate of the P-type transistor 10 is connected to the output terminal of the differential amplifier 9, and the resistor 11 is connected between the drain and the ground. The source of the P-type transistor 10 is connected to a power line. The differential amplifier 9 compares the REF value input into the (xe2x88x92) input terminal with the Sref value input into the (+) input terminal.
In the write mode, the OUT level of the write regulator 520 is determined by equation (2) based on the ratio of split by the resistance values R10, R11 of the resistor 11:
OUT={(R10+R11)/R10}xc3x97REF xe2x80x83xe2x80x83(2) 
Since, as described above, the REF level output from the band gap circuit 510 has been set so as not to have temperature dependence, the OUT level of the write regulator 520 is also set so as not to have temperature dependence.
In the verify mode, after writing (including writing after erase), write verification is carried out to judge whether or not information was correctly written. The memory cell of the nonvolatile memory is a kind of MOS (metal oxide semiconductor transistor) and thus is generally characterized in that the threshold voltage is high at low temperatures and decreases with raising the temperature. Therefore, in the verification after writing, setting in such a manner that the verify level is high at low temperatures and decreases with raising the temperature can realize advantageous verification because this setting conforms to the temperature characteristics of the threshold value of the memory cell. For this reason, a circuit is desired wherein the verify level decreases with raising the temperature.
The verify level having such temperature characteristics can be provided by adopting a reference voltage generator circuit having a construction shown in FIG. 2B described later wherein a reference voltage is generated in a band gap circuit having temperature dependence to provide a level necessary for the verify regulator circuit.
FIG. 2A is a schematic diagram showing the construction of a conventional reference voltage generator circuit for writing which is provided with a band gap circuit and a write regulator circuit, and FIG. 2B a schematic diagram showing the construction of a conventional reference voltage generator circuit for verification which is provided with a band gap circuit and a write regulator circuit.
Specifically, FIG. 2A shows a reference voltage generator circuit 601 for writing. The reference voltage generator circuit 601 for writing comprises a temperature-independent band gap (BGR) circuit 611 and a regulator circuit 612 for writing connected to the band gap circuit 611. A write reference voltage is output from the regulator circuit 612. Since the band gap circuit 611 does not have temperature dependence, the write reference voltage does not have temperature dependence.
FIG. 2B shows a verify reference voltage generator circuit 602. The verify reference voltage generator circuit 602 comprises a temperature-dependent band gap (BGR) circuit 611 and a verify regulator circuit 622 connected to the band gap circuit 621. A verify reference voltage is output from the regulator circuit 622. The band gap circuit 621 is set so that the output level has temperature dependence, that is, the output level decreases with raising the temperature. Therefore, the input of the verify regulator circuit 622 (output of the band gap circuit) changes upon a change in temperature, and this causes a change in the output level of the verify regulator circuit 622.
FIG. 3 shows the relationship between the output level of the write regulator circuit 612 shown in FIG. 2A and the temperature.
As described above, since the band gap circuit 611 does not have temperature dependence, the output voltage is constant independently of the temperature change (FIG. 3). Since the band gap circuit 611 does not have temperature dependence, the output level of the write regulator circuit 612 is also constant independently of the temperature change. Therefore, a constant level of voltage can be supplied to the drain and the gate independently of temperature environment under which the nonvolatile memory (memory cell) is placed. This enables writing to be carried out independently of the temperature.
FIG. 4 shows the relationship between the output level of the verify regulator circuit 622 shown in FIG. 2B and the temperature.
As is apparent from FIG. 4, since the band gap circuit 621 is set so that the output level has temperature dependence, the output level of the verify regulator circuit 622 varies depending upon the temperature, that is, the output level decreases with raising the temperature. Thus, by virtue of an advantage that a verify level according to the temperature characteristics of the threshold value of the memory cell can be obtained, advantageous conditions can be provided in the verification after writing.
In FIGS. 2A and 2B, the circuit construction of the write band gap circuit 611 is identical to that of the verify band gap circuit 621, and the circuit construction of the write regulator circuit 612 is identical to that of the verify regulator circuit 622. In this case, in order that the variation in the output level of the verify regulator circuit 622 is rendered identical to that of the level according to the temperature characteristics of the threshold value of the memory cell, the following measure is taken.
The temperature dependency xcex4(REF)/xcex4T of REF of the verify band gap circuit 621 is determined by the resistance values R7, R3 of the respective resistors 7, 3, the channel ratio [width/length=W/L], and the forward voltage VF of the diode 8, and is expressed by equation (3):
xcex4(REF)/xcex4T=(k/q)xc3x97ln[{(W4/L4)xc3x97(W2/L2)}/{(W1/L1)xc3x97(W5/L5)}]xc3x97{(W6/L6)xc3x97(W1/L1)}xc3x97(R7/R3)+xcex4(VF)/xcex4T xe2x80x83xe2x80x83(3) 
This equation (3) shows that the temperature dependency xcex4(VF)/xcex4T of the forward voltage VF of the diode 8 usually has a negative value, and the temperature dependency xcex4(REF)/xcex4T of REF can be set by the ratio of the resistance value R7 of the resistor 7 to the resistance value R3 of the resistor 3 shown in FIG. 1, i.e., R7/R3. That is, temperature dependence, such that the level is high at low temperatures and is low at high temperatures, can be imparted to the REF level through setting of the resistance values of the resistors 7 and 3.
In FIG. 1, the output (OUT) level of the write regulator 520 in the write mode is determined by equation (4) based on the split ratio of the resistance values R10, R11 of the resistor 11:
OUT={(R10+R11)/R10}xc3x97REF xe2x80x83xe2x80x83(4) 
Thus, a level necessary for verification can be obtained by the resistance value R10 and the resistance value 11 of the resistor 11. Further, since the temperature dependence of the REF level has been set so that the level is high at low temperatures and low at high temperatures, the temperature dependence of the output (OUT) level of the verify regulator is also such that the level is high at low temperatures and low at high temperatures.
Thus, in writing and verification, in order to provide write level and verify level which are different from each other in temperature dependence, two band gap circuits, i.e., a write band gap circuit and a verify band gap circuit, should be provided.
Japanese patent Laid-Open No. 154397/1999 discloses a prior art technique satisfying equation (3). According to this technique, the temperature dependence is rendered identical to that of the threshold voltage of the memory cell, and the output level is set so as to be high at low temperatures and low at high temperatures, whereby a lowering in read speed of the memory cell at low temperatures is reduced.
The reference voltage generator circuit of the conventional nonvolatile memory, however, suffers from the following problems.
(1) The band gap circuit has an analog construction, and a number of small MOS transistors are combined for accuracy improvement purposes, thereby suppressing the influence of a variation in threshold value of MOS transistors within a semiconductor wafer. For this reason, the layout area of one band gap circuit is large. In recent years, from the viewpoint of reducing the cost of IC (integrated circuit), there is an increasing tendency toward the development of techniques which have focused on a reduction in layout area. The large layout area of the band gap circuit obstructs this.
(2) In order to satisfy the requirement that, at the time of writing (erasing), the drain voltage and the gate voltage of the memory cell do not have temperature dependence and are always on a constant level so that the write characteristics are not dependent upon the temperature while, after writing (after erasing), a verify level according to the temperature characteristics of the threshold value of the memory cell is provided to ensure the margin in the verification, two band gap circuits, i.e., a band gap circuit for writing (erasing) and a band gap circuit for verification, should be provided. The provision of the two band gap circuits, however, further increases the layout area. This problem is also involved in the technique disclosed in Japanese patent Laid-Open No. 154397/1999.
Accordingly, it is an object of the invention to provide a reference voltage generator circuit for a nonvolatile memory which can realize temperature characteristics according to each mode while reducing the layout area by a level correction regulator circuit and a single band gap circuit.
According to the first feature of the invention, there is provided a reference voltage generator circuit for a nonvolatile memory, adapted for setting and applying a write voltage or an erase voltage and, in addition, a verify voltage to the gate of a memory cell according respectively to a write/erase mode and a verify/read mode of the nonvolatile memory, said reference voltage generator circuit comprising:
a band gap circuit for generating an output voltage according to the temperature characteristics of each of the modes and, in addition, switching the temperature characteristics for each mode; and
a level correction regulator circuit for generating a reference voltage for each of the modes based on the output voltage of the band gap circuit.
According to this construction, the band gap circuit generates an output voltage having temperature-output voltage characteristics corresponding to write/erase mode and an output voltage having temperature-output voltage characteristics corresponding to verify/read mode, and one of the output voltages is selected and output according to the modes. The output level of the selected output voltage is corrected for each mode by the level correction regulator circuit, and is then used as a reference voltage. Thus, since each reference voltage of the write/erase mode and the verify/read mode can be generated by one band gap circuit and one level correction regulator circuit, temperature characteristics according to each mode can be realized while reducing the layout area.